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STTS75
Digital temperature sensor and thermal watchdog
Features
Measures temperatures from -55C to +125C (-67F to +257F) - 2C accuracy from -25C to +100C (max) Low operating current: 75 A (typ) No external components required 2-wire I2C/SMBus-compatible serial interface - Selectable serial bus address allows connection of up to eight devices on the same bus Thermometer resolution is user-configurable from 9 (default) to 12 bits (0.5C to 0.0625C) 9-bit conversion time is 45 ms (typ) Programmable temperature threshold and hysteresis set points Wide power supply range-operating voltage range: 2.7 V to 5.5 V Power saving one-shot temperature measurement Power-up defaults permit standalone operation as thermostat Shutdown mode to minimize power consumption Separate open drain output pin operates as an interrupt or comparator/thermostat output (dual purpose event pin) Packages: - SO8 - MSOP8 (TSSOP8)
MSOP8 (TSSOP8) (DS) SO8 (M)

July 2008
Rev 9
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www.st.com 1
Contents
STTS75
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 1.3 Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Temperature sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 OS/INT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A2, A1, A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal alarm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fault tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus timeout feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 One-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Registers and register set formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Command/pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Over-limit temperature register (TOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hysteresis temperature register (THYS) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 3.3 3.4
Power-up default conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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STTS75 3.4.2 3.4.3 3.4.4 3.4.5
Contents Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 3.6
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 5 6 7 8 9 10
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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List of tables
STTS75
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fault tolerance setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Shutdown mode and one-shot mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Relationship between temperature and digital output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command/pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register pointers selection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Programmable resolution configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TOS and THYS register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STTS75 serial bus slave addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8 - 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 34 MSOP8 (TSSOP8) - 8-lead, thin shrink small package (3 mm x 3 mm) outline mechanical data35 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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STTS75
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Connections (SO8, TSSOP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical 2-wire interface connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OS output temperature response diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical 2-byte READ from preset pointer location (e.g. temp - TOS, THYS) . . . . . . . . . . . . 25 Typical pointer set followed by an immediate READ for 2-byte register (e.g. temp). . . . . . 25 Typical 1-byte READ from the configuration register with preset pointer . . . . . . . . . . . . . . 25 Typical pointer set followed by an immediate READ from the configuration register . . . . . 26 Configuration register WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TOS and THYS WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Temperature variation vs. voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8 - 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MSOP8 (TSSOP8) - 8-lead, thin shrink small package (3mm x 3mm) outline. . . . . . . . . . 35 Device topside marking information (SO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Device topside marking information (MSOP8/TSSOP8). . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Description
STTS75
1
Description
The STTS75 is a high-precision CMOS (digital) temperature sensor IC with a delta-sigma analog-to-digital (ADC) converter and an I2C-compatible serial digital interface (see Figure 1 on page 7). It is targeted for general applications such as personal computers, system thermal management, electronics equipment, and industrial controllers, and is packaged in the industry standard 8-lead TSSOP and SO8 packages (see Figure 2 on page 8). The device contains a band gap temperature sensor and programmable 9-to 12-bit ADC which monitor and digitize the temperature to a resolution up to 0.0625C. The STTS75 is typically accurate to (3C - max) over the full temperature measurement range of -55C to 125C with 2C accuracy in the -25C to +100C range. At power-up, the STTS75 defaults to 9-bit resolution for software compatibility with the STLM75. STTS75 is specified for operating at supply voltages from 2.7 V to 5.5 V. Operating at 3.3 V, the supply current is typically (75 A). The on-board delta sigma analog-to-digital converter (ADC) converts the measured temperature to a digital value that is calibrated in C; for Fahrenheit applications a lookup table or conversion routine is required. The STTS75 is factory-calibrated and requires no external components to measure temperature.
1.1
Serial communications
The STTS75 has a simple 2-wire I2C-compatible digital serial interface which allows the user to access the data in the temperature register at any time. It communicates via the serial interface with a master controller which operates at speeds up to 400 kHz. Three pins (A0, A1, and A2) are available for address selection, and enable the user to connect up to 8 devices on the same bus without address conflict. In addition, the serial interface gives the user easy access to all STTS75 registers to customize operation of the device.
1.2
Temperature sensor output
The STTS75 temperature sensor has a dedicated open drain over-limit signal/alert (OS/INT/Alert) output which features a thermal alarm function. This function provides a user-programmable trip and turn-off temperature. It can operate in either of two selectable modes:

Section 2.3: Comparator mode, and Section 2.4: Interrupt mode.
At power-up the STTS75 comes up in 9-bit mode and immediately begins measuring the temperature and converting the temperature to a digital value. The resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits which correspond to temperature increments of 0.5C, 0.25C, 0.125C, and 0.0625C, respectively.
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STTS75
Description The measured temperature value is compared with a temperature limit (which is stored in the 16-bit (TOS) READ/WRITE register), and the hysteresis temperature (which is stored in the 16-bit (THYS) READ/WRITE register). If the measured value exceeds these limits, the OS/INT pin is activated (see Figure 3 on page 8). Figure 1. Logic diagram
VDD
SDA(1) SCL O.S./INT(1) STDS75
A0 A1 A2
GND
AI11840
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details. Table 1.
Pin 1 2 3 4 5 6 7 8
Signal names
Symbol/Name SDA(1) SCL OS/INT(1) GND A2 A1 A0 VDD Type/direction Input/ Output Input Output Supply ground Input Input Input Supply power Description Serial data input/output Serial clock input Over-limit signal/interrupt alert output Ground Address2 input Address1 input Address0 input Supply voltage (2.7V to 5.5V)
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details.
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Description Figure 2. Connections (SO8, TSSOP8)
SDA(1) SCL O.S./INT(1) GND 1 2 3 4 8 7 6 5 VDD A0 A1 A2
AI11841
STTS75
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details. Figure 3. Functional block diagram
Temperature Sensor and Analog-to-Digital Converter (ADC) - VDD
Configuration Register Temperature Register THYS Set Point Register TOS Set Point Register
Pointer Register
Control and Logic Comparator
O.S.
A0 2-wire I2C Interface
SDA
A1 A2
SCL
GND
AI11833a
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STTS75
Description
1.3
Pin descriptions
See Figure 1 on page 7 and Table 1 on page 7 for a brief overview of the signals connected to this device.
1.3.1
SDA (open drain)
This is the serial data input/output pin for the 2-wire serial communication port.
1.3.2
SCL
This is the serial clock input pin for the 2-wire serial communication port.
1.3.3
OS/INT (open drain)
This is the over-limit signal/interrupt alert output pin. It is open drain, so it needs a pull-up resistor.
Note:
The open drain thermostat output that indicates if the temperature has exceeded userprogrammable limits (over/under temperature indicator).
1.3.4
GND
Ground; it is the reference for the power supply. It must be connected to system ground.
1.3.5
A2, A1, A0
A2, A1, and A0 are selectable address pins for the 3LSBs of the I2C interface address. They can be set to VDD or GND to provide 8 unique address selections.
1.3.6
VDD
This is the supply voltage pin, and ranges from +2.7 V to +5.5 V.
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Operation
STTS75
2
Operation
After each temperature measurement and analog-to-digital conversion, the STTS75 stores the temperature as a 16-bit two's complement number in the 2-byte temperature register. The most significant bit (S, Bit 15) indicates if the temperature is positive or negative:

for positive numbers S = 0, and for negative numbers S = 1.
The most recently converted digital measurement can be read from the temperature register at any time. Since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress. Bits 3 through 0 of the temperature register are hardwired to logic '0.' When the STTS75 is configured for 12-bit resolution, the 12MSBs (Bits 15 through 4) of the temperature register will contain temperature data. For 11-bit resolution, the 11MSBs (Bits 15 through 5) of the temperature register will contain data, and Bit 4 will read out as logic '0.' For 10-bit resolution, the 10MSbs (Bits 15 through 6) will contain data, and for 9-bit resolution the 9MSbs (Bits 15 through 7) will contain data and all unused LSBs will contain '0s.' Table 4 on page 15 gives examples of 12-bit resolution digital output data and the corresponding temperatures. The data is compared to the values in the TOS and THYS registers, and then the OS/INT is updated based on the result of the comparison and the operating mode. The number of TOS and THYS bits used during the thermostat comparison is equal to the conversion resolution set by the FT1 and FT0 bits in the configuration register. For example, if the resolution is 9 bits, only the 9MSbs of TOS and THYS will be used by the thermostat comparator. The alarm fault tolerance is controlled by the FTI and FTO bits in the configuration register. They are used to set up a fault queue. This prevents false tripping of the OS/INT pin when the STTS75 is used in a noisy environment (see Table 2 on page 14). The STTS75 also supports a special one-shot mode feature that performs a single temperature measurement and returns to shutdown mode. This is especially useful for lowpower applications. This features is accessed by first putting the device in shutdown mode, then enabling the one-shot mode (OSM) bit in the configuration register. The active state of the OS/INT output can be changed via the polarity (POL) bit in the configuration register. The power-up default is active-low. If the user does not wish to use the thermostat capabilities of the STTS75, the OS/INT output should be left floating. Note: If the thermostat is not used, the TOS and THYS registers can be used for general storage of system data.
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STTS75
Operation
2.1
Applications information
STTS75 digital temperature sensors are optimal for thermal management and thermal protection applications. They require no external components for operations except for pullup resistors on SCL, SDA, and OS/INT outputs. A 0.1 F bypass capacitor is recommended. The sensing device of STTS75 is the chip itself. The typical interface connection for this type of digital sensor is shown in Figure 4 on page 11. Intended applications include:

System thermal management Computers/disk drivers Electronics/test equipment Power supply modules Consumer products Battery management Fax/printers management Automotive Typical 2-wire interface connection diagram
Pull-up VDD VDD 10k STTS75 O.S./INT(1) SCL 0.1F VDD Pull-up VDD
Figure 4.
10k
10k
Master Device
A0 A1 A2
SDA(1) I2C Address = 1001000 (1001A2A1A0) GND
AI11832
1. SDA and OS/INT are open drain.
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Operation
STTS75
2.2
Thermal alarm function
The STTS75 thermal alarm function provides user-programmable thermostat capability and allows the STTS75 to function as a standalone thermostat without using the serial interface. The OS/INT output is the alarm output. This signal is an open drain output, and at power-up, this pin is configured with active-low polarity by default.
2.3
Comparator mode
In comparator mode, each time a temperature-to-digital (T-to-D) temperature conversion occurs, the new digital temperature is compared to the value stored in the TOS and THYS registers. If a fault tolerance number of consecutive temperature measurements are greater than the value stored in the TOS register, the OS/INT output will be activated. For example, if the FT1 and FT0 bits are equal to "10" (fault tolerance = 4), four consecutive temperature measurements must exceed TOS to activate the OS/INT output. Once the OS/INT output is active, it will remain active until the first time the measured temperature drops below the temperature stored in the THYS register. When the thermostat is in comparator mode, the OS/INT can be programmed to operate with any amount of hysteresis. The OS/INT output becomes active when the measured temperature exceeds the TOS value a consecutive number of times as defined by the FT1 and FT0 fault tolerance (FT) bits in the configuration register. The OS/INT then stays active when the temperature falls below the value stored in THYS register for a consecutive number of times as defined by the fault tolerance bits (FT1 and FT0). Putting the device into shutdown mode does not clear OS/INT in comparator mode.
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STTS75
Operation
2.4
Interrupt mode
In Interrupt mode, the OS/INT output first becomes active when the measured temperature exceeds the TOS value a consecutive number of times equal to the FT value in the configuration register. Once activated, the OS/INT can only be cleared by either putting the STTS75 into shutdown mode or by reading from any register (temperature, configuration, TOS, or THYS) on the device. Once the OS/INT has been deactivated, it will only be reactivated when the measured temperature falls below the THYS value a consecutive number of times equal to the FT value. Figure 5 illustrates typical OS output temperature response for STTS75 configured to have a fault tolerance of 2. The interrupt/clear process is cyclical between TOS and THYS. Figure 5. OS output temperature response diagram
TOS Temperature THYS Inactive OS Output - Comparator mode Active Inactive OS Output - Interrupt mode Active (1) (1) (1)
Conversions
AI12224b
1. This assumes that a READ has occurred.
Note:
The STTS75 is configured to have a fault tolerance of 2 in this example.
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Operation
STTS75
2.5
Fault tolerance
For both comparator and interrupt modes, the alarm "fault tolerance" setting plays a role in determining when the OS/INT output will be activated. Fault tolerance refers to the number of consecutive times an error condition must be detected before the user is notified. Higher fault tolerance settings can help eliminate false alarms caused by noise in the system. The alarm fault tolerance is controlled by the bits (Bits 4 and 3) in the configuration register. These bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in Table 2. At power-up, these bits both default to logic '0.' Table 2.
FT1 0 0 1 1
Fault tolerance setting
FT0 0 1 0 1 STTS75 (consecutive faults) 1 2 4 6 Comments Power-up default
2.6
Shutdown mode
For power-sensitive applications, the STTS75 offers a low-power shutdown mode. The SD bit in the configuration register controls shutdown mode. When SD is changed to login '1,' the conversion in progress will be completed and the result stored in the temperature register, after which the STTS75 will go into a low-power standby state. The OS/INT output will be cleared if the thermostat is operating in Interrupt mode and the OS/INT will remain unchanged in comparator mode. The 2-wire interface remains operational in shutdown mode, and writing a '0' to the SD bit returns the STTS75 to normal operation. Table 3. Shutdown mode and one-shot mode description
One-shot mode (OSM) (bit 7) 0 0 1 1 Shutdown (SD) (bit 0) 0 1 0 1
Operational mode Continuous conversion Shutdown (1) Continuous conversion One-shot
1. The shutdown command needs to be programmed before sending a one-shot command.
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STTS75
Operation
2.7
Temperature data format
Table 4 shows the relationship between the output digital data and the external temperature for 12-bit resolution. Temperature data for temperature, TOS and THYS registers is represented by 9-bit, 10-bit, 11-bit, and 12-bit depending upon the resolution bits RC1, RC0 (Bits 6 and 5) in the configuration register (see Table 7 on page 18). The default resolution is 9-bits. The left-most bit in the output data stream controls temperature polarity information for each conversion. If the sign bit is '0', the temperature is positive and of the sign bit is '1', the temperature is negative. Table 4. Relationship between temperature and digital output
Digital output (HEX)
Temperature Sign
Number of bits used by conversion resolution
9
10
11
12
Always zero 0000
12-bit resolution 11-bit resolution 10-bit resolution 9-bit resolution +125C +25.0625C +10.125C +0.5C 0C -0.5C -10.25C -25.0625C -55C 0 0 0 0 0 1 1 1 1 111 001 000 000 000 111 111 110 100 1101 1001 1010 0000 0000 1111 0101 0110 1001 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7D00 1910 0A20 0080 0000 FF80 F5E0 E6F0 C900
2.8
Bus timeout feature
The STTS75 supports an SMBus compatible timeout function which will reset the serial I2C/SMBus interface if SDA is held low for a period greater than the timeout duration between a START and STOP condition. If this occurs, the device will release the bus and wait for another START condition.
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Operation
STTS75
2.9
One-shot mode
STTS75 supports a one-shot temperature measurement mode. This is invoked by putting the device in shutdown mode (SD bit 0 in the configuration register is set to `1') and writing a `1' to the OSM (bit 7) to start a single temperature conversion. STTS75 returns to the shutdown state after completion of the single conversion. This is useful to reduce power consumption when continuous monitoring is not needed. When the configuration register is read, the OSM bit will read `0'.
16/39
STTS75
Functional description
3
Functional description
The STTS75 registers have unique pointer designations which are defined in Table 6 on page 17. Whenever any READ/WRITE operation to the STTS75 register is desired, the user must "point" to the device register to be accessed. All of these user-accessible registers can be accessed via the digital serial interface at anytime (see Serial interface on page 21), and they include:

Command register/address pointer register Configuration register Temperature register Over-limit signal temperature register (TOS) Hysteresis temperature register (THYS)
3.1
3.1.1
Registers and register set formats
Command/pointer register
The most significant bits (MSBs) of the command register must always be zero. Writing a '1' into any of these bits will cause the current operation to be terminated (see Table 5). The command register retains pointer information between operations. Therefore, this register only needs to be updated once for consecutive READ operations from the same register. All bits in the command register default to '0' at power-up. Table 5.
MSB Bit7 0 Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 P1 Pointer
Command/pointer register format
LSB Bit0 P0
Table 6.
Pointer value (H) 00 01 02
Register pointers selection summary
P1 P0 Name Description Temperature register Configuration register Hysteresis register Overtemperature shutdown Width Type (bits) (R/W) 16 8 16 Read only R/W R/W Power-on default N/A 00 4800 Default = 75C Set point for overtemperature shutdown (TOS) limit default = 80C Comments To store measured temperature data
0 0 1
0 1 0
TEMP CONF THYS
03
1
1
TOS
16
R/W
5000
17/39
Functional description
STTS75
3.1.2
Configuration register
The configuration register is used to store the device settings such as device operation mode, OS/INT operation mode, OS/INT polarity, and OS/INT fault queue. The configuration register allows the user to program various options such as conversion resolution (see Table 8), thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. The user has READ/WRITE access to all of the bits in the configuration register. The entire register is volatile and thus powers-up in its default state only. Table 7.
Byte Bit7 STTS75 Default Keys: OSM 0 Bit6 RC1 0 Bit5 RC0 0 Bit4 FT1 0 Bit3 FT0 0 Bit2 POL 0 Bit1 M 0 Bit0 SD 0
Configuration register format
MSB LSB
SD = shutdown control bit M = thermostat mode(1)
(2)
FT1 = fault tolerance1 bit RC0 = resolution conversion0 bit RC1 = resolution conversion1 bit OSM = one-shot mode bit
POL = output polarity
FT0 = fault tolerance0 bit
1. Indicates operation mode; 0 = comparator mode, and 1 = interrupt mode (see Comparator mode and Interrupt mode on page 13). 2. The OS/INT is active-low ('0').
Table 8.
RC1 0 0 1 1
Programmable resolution configurations
RC0 0 1 0 1 Resolution 9-bit 10-bit 11-bit 12-bit 0.5C 0.25C 0.125C 0.0625C Conversion time (max) 85 ms 170 ms 340 ms 680 ms Remarks Default resolution
18/39
STTS75
Functional description
3.1.3
Temperature register
The temperature register is a two-byte (16-bit) "Read only" register (see Table 9 on page 19). Digital temperatures from the ADC are stored in the temperature register in two's complement format, and the contents of this register are updated each time the A/D conversion is finished. The user can read data from the temperature register at any time. When a T-to-D conversion is completed, the new data is loaded into a comparator buffer to evaluate fault conditions and will update the temperature register if a read cycle is not ongoing. If a READ is ongoing, the previous temperature will be read. Accessing the STTS75 continuously without waiting at least one conversion time between communications will prevent the device from updating the temperature register with a new temperature conversion result. Consequently, the STTS75 should not be accessed continuously with a wait time of less than tCONV (max). Depending on the A/D conversion resolution, the 9-, 10-, 11- or 12-bit MSBs of the register will contain temperature data. All unused bits following the digital temperature will be zero. The MSB (Bit 15) of the temperature register denotes whether the temperature data is positive or negative. A '0' in Bit 15 is positive and a '1' is negative. Table 9.
Bytes MSB Bits 15 STTS75 SB 14 13 12 11 10 9 8 7 9-bit LSB 6 5 4 321 0 0 10-bit 11-bit 12-bit 000 LSB LSB LSB
Temperature register format
MS byte THSB LS byte TLSB LSB
TMSB TD TD TD TD TD TD
Keys:
SB = two's complement sign bit TMSB = temperature MSB TLSB = temperature LSB TD = temperature data
3.1.4
Over-limit temperature register (TOS)
The TOS register is a two-byte (16-bit) READ/WRITE register that stores the userprogrammable upper trip-point temperature for the thermal alarm in two's complement format (see Table 10 on page 20). This register defaults to 80C at power-up (i.e., 0101 0000 0000 0000). The format of the TOS register is identical to that of the temperature register. The 4 LSBs of the TOS register are hardwired to zero, so data written to these register bits will be ignored. The MSB position contains the sign bit for the digital temperature and Bit14 contains the temperature MSB. The resolution setting for the A/D conversion determines how many bits of the TOS register are used by the thermal alarm. For example, for 9-bit conversions, the trip-point temperature is defined by the 9 MSBs of the TOS register, and all remaining bits are "Don't cares."
19/39
Functional description
STTS75
3.1.5
Hysteresis temperature register (THYS)
THYS register is a two-byte (16-bit) READ/WRITE register that stores the userprogrammable lower trip-point temperature for the thermal alarm in two's complement format (see Table 10). This register defaults to 75C at power-up (i.e., 0100 1011 0000 0000). The format of this register is the same as that of the temperature register. The 4 LSBs of the THYS register are hardwired to zero, so data written to these bits is ignored. The MSB position contains the sign bit for the digital temperature and Bit14 contains the temperature MSB. The resolution setting for the A/D conversion determines how many bits of the THYS register are used by the thermal alarm. For example, for 9-bit conversions, the hysteresis temperature is defined by the 9 MSBs of the THYS register, and all remaining bits are "Don't cares." Table 10.
Bytes MSB Bits 15 STTS75 SB 14 13 12 11 10 9 8 7 9-bit LSB 6 5 4 321 0 0 10-bit 11-bit 12-bit 000 LSB LSB LSB
TOS and THYS register format
MS byte THSB LS byte TLSB LSB
TMSB TD TD TD TD TD TD
Keys:
SB = two's complement sign bit TMSB = temperature MSB TLSB = temperature LSB TD = temperature data
3.2
Power-up default conditions
The STTS75 always powers up in the following default states:

Thermostat mode = comparator mode Polarity = active-low Fault tolerance = 1 fault (i.e., relevant bits set to '0' in the configuration register) TOS = 80C THYS = 75C OSM = 0 (disabled) Register pointer = 00 (temperature register) Conversion resolution = 9-bit (i.e., RC0 = 0 and RC1 = 0 in the configuration register; see Table 7 on page 18)
Note:
After power-up these conditions can be reprogrammed via the serial interface.
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STTS75
Functional description
3.3
Serial interface
Writing to and reading from the STTS75 registers is accomplished via the two-wire serial interface protocol which requires that one device on the bus initiates and controls all READ and WRITE operations. This device is called the "master" device. The master device also generates the SCL signal which provides the clock signal for all other devices on the bus. These other devices on the bus are called "slave" devices. The STTS75 is a slave device (see Table 11). Both the master and slave devices can send and receive data on the bus. During operations, one data bit is transmitted per clock cycle. All operations follow a repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.
Note:
There are no unused clock cycles during any operation, so there must not be any breaks in the data stream and ACKs/NACKs during data transfers. Conversely, having too few clock cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register occurs. Table 11.
MSB Bit7 1 Bit6 0 Bit5 0 Bit4 1 Bit3 A2 Bit2 A1 Bit1 A0
STTS75 serial bus slave addresses
LSB Bit0 R/W
3.4
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined (see Figure 6 on page 22):
3.4.1
Bus not busy
Both data and clock lines remain high.
3.4.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
3.4.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
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Functional description
STTS75
3.4.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." Figure 6. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
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STTS75
Functional description
3.4.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse (see Figure 7 on page 23). A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 7. Acknowledgement sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
23/39
Functional description
STTS75
3.5
READ mode
In this mode the master reads the STTS75 slave after setting the slave address (see Figure 8). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. There are two READ modes:

Preset pointer locations (e.g. Temperature, TOS and THYS registers), and Pointer setting (the pointer has to be set for the register that is to be read)
Note:
The Temperature register pointer is usually the default pointer. These modes are shown in the READ mode typical timing diagrams (see Figure 9, Figure 10, and Figure 11 on page 25). Figure 8. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
0
0
1
A2 A1 A0
AI12226
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LSB
STTS75 Figure 9.
Functional description Typical 2-byte READ from preset pointer location (e.g. temp - TOS, THYS)
1 9 1 9 1 9
1
0
0
1
A2 A1 A0
R
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Start by Master
Address Byte ACK by STTS75
Most Significant Data Byte ACK by Master
Least Significant Data Byte
Stop Cond. by No ACK Master by Master
AI12281b
Figure 10. Typical pointer set followed by an immediate READ for 2-byte register (e.g. temp)
1 9 1 9
1
0
0
1
A2 A1 A0
W
0
0
0
0
0
0
D1 D0
Start by Master
Address Byte ACK by STTS75
1 9 1
Pointer Byte ACK by STTS75
9 1 9
1
0
0
1
A2 A1 A0
R
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Repeat Start by Master
Address Byte ACK by STTS75
Most Significant Data Byte ACK by Master
Least Significant Data Byte
Stop Cond. No ACK by by Master Master
AI12282b
Figure 11. Typical 1-byte READ from the configuration register with preset pointer
1 9 1 9
1
0
0
1
A2 A1 A0
R
D7 D6 D5 D4 D3 D2 D1 D0
Start by Master
Address Byte ACK by STTS75
Data Byte
Stop Cond. by No ACK Master by Master
AI12283b
25/39
Functional description
STTS75
3.6
WRITE mode
In this mode the master transmitter transmits to the STTS75 slave receiver. Bus protocol is shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address will follow and is to be written to the on-chip address pointer. These modes are shown in the WRITE mode typical timing diagrams (see Figure 12, and Figure 13, and Figure 14 on page 27). Figure 12. Typical pointer set followed by an immediate READ from the configuration register
1 9 1 9
1
0
0
1
A2 A1 A0
W
0
0
0
0
0
0
D1 D0
Start by Master
Address Byte ACK by STTS75
Pointer Byte ACK by STTS75
1
9
1
9
1
0
0
1
A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Repeat Start by Master
Address Byte ACK by STTS75
Data Byte
Stop Cond. No ACK by by Master STTS75
AI12279b
Figure 13. Configuration register WRITE
1 9 1 9 1 9
1
0
0
1
A2 A1 A0
W
0
0
0
0
0
0
D1 D0
0
0
0
D4 D3 D2 D1 D0
Start by Master
Address Byte ACK by STTS75
Pointer Byte ACK by STTS75
Configuration Byte
Stop Cond. ACK by by Master STTS75
AI12280b
26/39
STTS75 Figure 14. TOS and THYS WRITE
1 9 1 9
Functional description
1
0
0
1
A2 A1 A0
W
0
0
0
0
0
0
D1 D0
Start by Master
Address Byte ACK by STTS75
Pointer Byte ACK by STTS75
1
9
1
9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Most Significant Data Byte ACK by STTS75
Least Significant Data Byte ACK by STTS75
Stop Cond. by Master
AI12284b
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Typical operating characteristics
STTS75
4
Typical operating characteristics
Figure 15. Temperature variation vs. voltage
140 120 100
Temperature (C)
80 60 40 20 0 -20 -40 -60 2 3 4 5 6
-20 0.5 85 110 125
Voltage (V)
AI12258
28/39
STTS75
Maximum rating
5
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 12.
Symbol TSTG TSLD(1) VIO VDD VOUT IO PD
Absolute maximum ratings
Parameter Storage temperature Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output voltage Output current Power dissipation Value -60 to 150 260 VDD +0.5 7.0 VDD + 0.5 10 320 Unit C C V V V mA mW
1. Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds).
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DC and AC parameters
STTS75
6
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 13. Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 13. Operating and AC measurement conditions
Parameter Supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing reference voltages STTS75 2.7 to 5.5 -55 to 125 5 0.2 to 0.8VDD 0.3 to 0.7VDD Unit V C ns V V
30/39
STTS75 Table 14.
Sym VDD
DC and AC parameters DC and AC characteristics
Description Supply voltage VDD supply current, active temperature conversions IDD VDD supply current, communication only Standby supply current, serial port inactive Accuracy for corresponding range 2.7 V VDD 5.5 V Resolution Test Condition(1) TA = -55 to +125C VDD = 3.3 V TA = 25C TA = 25C -25C < TA < 100 -55C < TA < 125 9 to 12-bit temperature data 9 10 tCONV Conversion time 11 12 TOS THYS VOL1 VIH VIL VOL2 CIN Over-temperature shutdown Hysteresis OS/INT saturation voltage (VDD = 5V) Input logic high Input logic low Output logic low (SDA) Capacitance Default value Default value 4 mA sink current Digital pins (SCL, SDA, A2-A0) Digital pins IOL2= 3 mA 5 0.5 x VDD -0.45 0.5 9 45 90 180 360 80 75 0.5 VDD + 0.5 0.3 x VDD 0.4 Min 2.7 75 Typ(2) Max 5.5 100 100 1.0 Unit V A A A C C C bits ms ms ms ms C C V V V V pF
IDD1
2.0 3.0
0.0625 12 85 170 340 680
1. Valid for ambient operating temperature: TA = -55 to 125C; VDD = 2.7 V to 5.5 V (except where noted). 2. Typical number taken at VDD = 3.3 V, TA=25C
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DC and AC parameters Figure 16. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tF tHD:STA
STTS75
tSU:STO
AI00589
Table 15.
Sym fSCL tBUF tF tHD:DAT(2) tHD:STA tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO
AC characteristics
Parameter(1) SCL clock frequency Time the bus must be free before a new transmission can start SDA and SCL fall time Data hold time START condition hold time (after this period the first clock pulse is generated) Clock high period Clock low period SDA and SCL rise time Data setup time START condition setup time (only relevant for a repeated start condition) STOP condition setup time 100 600 600 75 325 600 600 1.3 300 Min 0 1.3 300 0.9 Max 400 Unit kHz s ns s ns ns s ns ns ns ns ns
tTIME-OUT SDA low time for reset of serial interface (3)
1. Valid for ambient operating temperature: TA = -55 to 125C; VDD = 2.7 V to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. 3. For SMBus compatibility STTS75 supports bus timeout. Holding the SDA line low for a period greater than timeout duration will cause STTS75 to reset the SDA line to the state of serial bus communication (SDA high).
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STTS75
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
33/39
Package mechanical data Figure 17. SO8 - 8-lead plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
STTS75
A ccc c
D
E1
1
E A1 L L1
SO-A
Note:
Drawing is not to scale. Table 16.
Sym Typ A A1 A2 b c ccc D E E1 e h k L L1 1.04 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 0.10 1.25 0.28 0.17 0.48 0.23 0.10 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 Min Max 1.75 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
SO8 - 8-lead plastic small outline package mechanical data
mm inches
34/39
STTS75
Package mechanical data Figure 18. MSOP8 (TSSOP8) - 8-lead, thin shrink small package (3mm x 3mm) outline
D
8
5 E1 E
c
1
4
k
A1 A ccc b e A2
L L1
L2
E3_ME
Note:
Drawing is not to scale. Table 17. MSOP8 (TSSOP8) - 8-lead, thin shrink small package (3 mm x 3 mm) outline mechanical data
mm Sym Typ A A1 A2 b c D E E1 e L L1 L2 k ccc 3.00 4.90 3.00 0.65 0.60 0.95 0.25 0 8 0.10 0.40 0.80 0.85 0.00 0.75 0.22 0.08 2.80 4.65 2.80 Min Max 1.10 0.15 0.95 0.40 0.23 3.20 5.15 3.10 0.118 0.193 0.118 0.026 0.024 0.037 0.010 0 8 0.004 0.016 0.032 0.034 0.000 0.030 0.009 0.003 0.110 0.183 0.110 Typ Min Max 0.043 0.006 0.037 0.016 0.009 0.126 0.203 0.122 inches
35/39
Part numbering
STTS75
8
Part numbering
Table 18.
Example:
Ordering information scheme
STTS75 M 2 F
Device type STTS75
Package M = SO8 DS = MSOP8 (TSSOP8)
Temperature range 2 = -55 to 125C
Shipping method F = ECOPACK(R) package, tape & reel E = ECOPACK(R) package, tube
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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STTS75
Package marking information
9
Package marking information
Figure 19. Device topside marking information (SO8)
STTS75M2 EPYWW(1)
ai13912
1. Traceability codes E = Additional information P = Plant code Y = Year WW = Work Week
Figure 20. Device topside marking information (MSOP8/TSSOP8)
TS75 PYWW(1)
ai13913
1. Traceability codes P = Plant code Y = Year WW = Work Week
37/39
Revision history
STTS75
10
Revision history
Table 19. Document revision history
Revision 1 2 Initial release. Update features (cover page), DC and AC characteristics (Table 14), package mecanical information (Figure 17, Table 16, Figure 18, Table 17) and part numbering (Table 18). Update cover page (package information); Section 2: Operation; Section 2.3: Comparator mode; Section 2.8: Bus timeout feature; Table 14; package mechanical data (Figure 18 and Table 17); and part numbering (Table 18). Package information (DFN8) added to cover page, Figure 2, Figure 19, Table 18. AddedSection 9: Package marking information. Updated Table 12, 13, 15, and 18. Updated cover page, Figure 19, 22, Table 14, and 18. Updated cover page, Figure 4, Section 3.1.3, Section 3.1.5, Table 8, 14, and 15. Updated cover page, document status upgraded to full datasheet, updated Figure 2, Section 7, 8, 9. Minor text changes; added Section 2.9: One-shot mode; updated Section 3.1.3: Temperature register. Updated cover page and Table 18. Changes
Date 14-Jun-2006 22-Jan-2007
01-Mar-2007
3
18-Apr-2007 09-May-2007 16-May-2007 06-Jun-2007 07-Jul-2008 18-Jul-2008
4 5 6 7 8 9
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STTS75
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